A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise

@article{Morie2013A75,
  title={A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise},
  author={Takashi Morie and Takuji Miki and Kazuo Matsukawa and Yoji Bando and Takeshi Okumoto and Koji Obata and Shiro Sakiyama and Shiro Dosho},
  journal={2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers},
  year={2013},
  pages={272-273}
}
SAR-ADC power efficiency has improved due to its digitally oriented nature that utilizes the high switching speed of nanometer CMOS processes. In recent reports, time-interleaving techniques and multi-bit-per-cycle conversion have boosted speed to the GHz sampling range at low power consumption. However, to achieve SNR of >70dB at moderate sampling speed, SARs still need a lot of power, namely tens of mW [1-2]. In [1], a very high SNR of 90dB is achieved by a stage to amplify residue charge… CONTINUE READING

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