A 70ns high density CMOS DRAM

  title={A 70ns high density CMOS DRAM},
  author={R. Chwang and M. Choi and D. Creek and S. Stern and P. Pelley and J. Schutz and M. Bohr and P. Warkentin and K. Yu},
  journal={1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  • R. Chwang, M. Choi, +6 authors K. Yu
  • Published 1983
  • Computer Science
  • 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
A 64K DRAM, processed in N-well CMOS technology with 137μm2double poly P-channel memory cells, will be reported. Access time is 70ns at 150mW. Operating margins, SER and redundancy repairability will be discussed. 
17 Citations
A sub 100ns 256K DRAM in CMOS III technology
  • R. Kung, A. Mohsen, +6 authors S. Chou
  • Engineering
  • 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
  • 1984
A sub 100ns 256Kb CMOS DRAM with 25μW standby power, 25MHz ripple mode and static column mode data rate will be reported. Channel length is 1μm and the SER is below 0.1%/1KHr.
A 64K Pseudo Static RAM with N-Well CMOS Technology
A 64K Pseude static RAM has been realized using direct step-on-wafer lithography technology and dry processing technology. Most outstanding feature of this RAM is low supply current during selfExpand
A 16K CMOS PROM with polysilicon fusible links
  • L.R. Metzger
  • Engineering
  • IEEE Journal of Solid-State Circuits
  • 1983
A 16K synchronous CMOS PROM with polysilicon fusible links and a 2K-word by 8-bit organization is described. The memory cell makes use of the vertical bipolar NPN that is inherent in the p-well CMOSExpand
A Submicrometer Megabit DRAM Process Technology Using Trench Capacitors
An experimental 1-Mbit DRAM with a cell size of 20 /spl mu/m/sup 2/ is successfully developed by using technologies developed. Expand
Plate-noise analysis of an on-chip generated half-VDD biased-plate PMOS cell in CMOS DRAMs
An on-chip generated half-VDD bias for the memory-cell plate is used in CMOS DRAMS to reduce the electric field in the storage insulator such that higher capacitor reliability can be achieved or aExpand
Evolution of the MOSFET dynamic RAM—A personal view
  • R. Dennard
  • Engineering
  • IEEE Transactions on Electron Devices
  • 1984
The early conceptual stages and key elements in the development of the one-device MOSFET dynamic RAM are reviewed from the personal perspective of the author. Future miniaturization to the level of ¼Expand
Offset word line architecture for scaling DRAMs to the Gigabit level
Scaling technology for future DRAM generations has become increasingly more difficult. A key limitation is the non-scaling of threshold voltage Vt. Various techniques have been investigated toExpand
Impact of processing technology on DRAM sense amplifier design
Sense amplifier design is critical to DRAM performance. As DRAM chip capacity has increased, different sensing schemes have been employed. The purpose of this work is to explain impacts of processingExpand
A 60uA Standby Power 32k × 8 Pseudo-Static RAM
Standby power of a 32k × 8 pseudo-static RAM has been reduced to 60uA using an expanded internal refresh interval, a reduced oscillating frequency by a back bias generator, and other power savingExpand
A multiplexed 4 Mbit bubble memory device
A 4-M bit magnetic bubble memory has been designed and demonstrated which is architecturally compatible with an 1-Mbit memory and able to achieve user software compatibility and pin-for-pin interchangeability. Expand


A HI-CMOSII 8K × 8b static RAM
A fully-static 8K×8b RAM using HICMOSII technology with a typical address access time of 65ns and power dissipation of 200mW will be discussed. To improve manufacturing yield a laser redundancyExpand
A 150ns CMOS 64K EPROM using N-well technology
THE STRONG NEED for low power, high density, high perform­ance CMOS EPROMs has been established by the evolution of faster and denser low power microprocessors, due to their de­ pendence onExpand