A 70ns high density CMOS DRAM

@article{Chwang1983A7H,
  title={A 70ns high density CMOS DRAM},
  author={R. Chwang and M. Choi and D. Creek and S. Stern and P. Pelley and J. Schutz and M. Bohr and P. Warkentin and K. Yu},
  journal={1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  year={1983},
  volume={XXVI},
  pages={56-57}
}
  • R. Chwang, M. Choi, +6 authors K. Yu
  • Published 1983
  • Computer Science
  • 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
A 64K DRAM, processed in N-well CMOS technology with 137μm2double poly P-channel memory cells, will be reported. Access time is 70ns at 150mW. Operating margins, SER and redundancy repairability will be discussed. 
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