A 7.65-mW 5-bit 90-nm 1-Gs/s Folded Interpolated ADC Without Calibration

@article{DAmico2014A75,
  title={A 7.65-mW 5-bit 90-nm 1-Gs/s Folded Interpolated ADC Without Calibration},
  author={Stefano D'Amico and Giuseppe Cocciolo and Annachiara Spagnolo and Marcello De Matteis and Andrea Baschirotto},
  journal={IEEE Transactions on Instrumentation and Measurement},
  year={2014},
  volume={63},
  pages={295-303}
}
Power consumption of high-speed low-resolution analog-to-digital converters (ADCs) can be reduced by means of calibration. However, this solution has some drawbacks such as time slot allocation for calibration and die area increase. This paper presents a 5-bit 1-Gs/s ADC without calibration, fabricated in 90-nm CMOS. Low power consumption has been ensured by operating at both architecture and comparator levels. A folded interpolated architecture has been adopted. However, compared to standard… CONTINUE READING