A 7.6 mW 1.75 GS/s 5 bit flash A/D converter in 90 nm digital CMOS

@article{Verbruggen2008A7M,
  title={A 7.6 mW 1.75 GS/s 5 bit flash A/D converter in 90 nm digital CMOS},
  author={Bob Verbruggen and Piet Wambacq and M. Kuijk and Geert Van der Plas},
  journal={2008 IEEE Symposium on VLSI Circuits},
  year={2008},
  pages={14-15}
}
A 5 bit 1.75 GS/s flash ADC is realized in 90 nm CMOS. It uses a comparator array with built-in imbalance and offset calibration to lower power consumption. The SNDR is 30.9 dB at low frequencies and gradually degrades to 28.2 dB at 2 GHz. The ADC occupies 280 mum by 110 mum and draws only 7.6 mA from a 1 V supply yielding an energy efficiency of 0.15 pJ/conversion step. 
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