A 7.1fJ/conv.-step 88dB-SFDR 12b SAR ADC with energy-efficient swap-to-reset

@article{Liu2016A78,
  title={A 7.1fJ/conv.-step 88dB-SFDR 12b SAR ADC with energy-efficient swap-to-reset},
  author={Maoqiang Liu and Arthur H. M. van Roermund and Pieter Harpe},
  journal={ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference},
  year={2016},
  pages={409-412}
}
In this work, a novel DAC reset scheme for SAR ADCs is proposed, which eliminates the reset energy consumption. This reset energy consumption can be significant and is seldom optimized in low power switching schemes. The scheme can be applied to all differentially reset and switched DACs. This `swap-to-reset' operation is applied to the 2 MSBs of a 12b SAR ADC fabricated in 65nm CMOS, resulting in an energy saving of 33% for the DAC or 18% for the whole ADC. Besides swapping, rotation is also… CONTINUE READING

Figures, Tables, Results, and Topics from this paper.

Key Quantitative Results

  • This `swap-to-reset' operation is applied to the 2 MSBs of a 12b SAR ADC fabricated in 65nm CMOS, resulting in an energy saving of 33% for the DAC or 18% for the whole ADC.
  • This ‘swap-to-reset’ operation is applied to the 2 MSBs of a 12b SAR ADC fabricated in 65nm CMOS, resulting in an energy saving of 33% for the DAC or 18% for the whole ADC.

Citations

Publications citing this paper.
SHOWING 1-10 OF 11 CITATIONS

Backtracking Algorithm-Aided Design of a 10-Bit SAR ADC

VIEW 4 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

Speed & Resolution Enhancement of 12-Bit SAR ADC

  • 2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS)
  • 2018

A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator

  • 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
  • 2017

Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC

  • 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
  • 2017

High resolution and linearity enhanced SAR ADC for wearable sensing systems

  • 2017 IEEE International Symposium on Circuits and Systems (ISCAS)
  • 2017

References

Publications referenced by this paper.
SHOWING 1-10 OF 11 REFERENCES

A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS

  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • 2016
VIEW 1 EXCERPT

15.4 A 0.8V 10b 80kS/s SAR ADC with duty-cycled reference generation

  • 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
  • 2015
VIEW 1 EXCERPT

11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR

  • 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
  • 2014
VIEW 2 EXCERPTS

11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS

  • 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
  • 2014
VIEW 2 EXCERPTS

11.3 A 10b 0.6nW SAR ADC with data-dependent energy savings using LSB-first successive approximation

  • 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
  • 2014
VIEW 1 EXCERPT

A 26 μW 8-bit 10 MS/s asynchronous SAR ADC for low energy radios

P. Harpe, C. Zhou, +4 authors H. de Groot
  • IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1585-1595, Jul. 2011.
  • 2011
VIEW 2 EXCERPTS