A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm$^{2}$ 65 nm CMOS Circuit

@article{Prefasi2011A7M,
  title={A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm\$^\{2\}\$  65 nm CMOS Circuit},
  author={Enrique Prefasi and Susana Pat{\'o}n and Luis Hern{\'a}ndez},
  journal={IEEE Journal of Solid-State Circuits},
  year={2011},
  volume={46},
  pages={1562-1574}
}
This work presents an area- and power-efficient realization of a new time-encoding oversampling converter (TEOC) consisting of a third-order continuous time (CT) loop filter and a self-oscillating pulse-width modulator (PWM). The modulator displays similar performance to that of a standard multibit CT-ΣΔ modulator but has the complexity of a single bit design. The time-encoding quantizer (TEQ) is implemented inside a ΣΔ modulator by replacing a multibit quantizer. An innovative TEQ is used to… CONTINUE READING
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A 9 b 100 MS/s 1.46 mW SARADC in 65 nm CMOS

  • Y. Chen, S. Tsukamoto, T. Kuroda
  • IEEE A-SSCCDig. Tech. Papers, Nov. 2009, pp. 145…
  • 2009
2 Excerpts

A single bit 6 . 8 mW 10 MHz power - optimized continuous - time with 67 dB DR in 90 nm CMOS , ” in

  • S. Pavan
  • Proc . ESSCIRC
  • 2009

A single bit 6.8 mW 10MHz power-optimized continuous-time with 67 dB DR in 90 nm CMOS

  • P. Crombez
  • Proc. ESSCIRC 2009, Sep. 2009, pp. 336–339.
  • 2009

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