A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

@article{Oh2010A7G,
  title={A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction},
  author={Tae-Young Oh and Young-Soo Sohn and Seung-Jun Bae and Min-Sang Park and Ji-Hoon Lim and Yong-Ki Cho and Dae-Hyun Kim and Dong-Min Kim and Hye Ran Kim and Hyun-Joong Kim and Jin-Hyun Kim and Jin-Kook Kim and Young-Sik Kim and Byeong-Cheol Kim and Sang-Hyup Kwak and Jae-Hyung Lee and Jae-young Lee and Chang-Ho Shin and Yun-Seok Yang and Beom-Sig Cho and Sam-Young Bang and Hyang-Ja Yang and Young-Ryeol Choi and Gil-Shin Moon and Cheol-Goo Park and Seokwon Hwang and Jeong-Don Lim and Kwang-Il Park and Joo-Sun Choi and Young-Hyun Jun},
  journal={IEEE Journal of Solid-State Circuits},
  year={2010},
  volume={46},
  pages={107-118}
}
This paper describes a 1 Gbit GDDR5 SDRAM with enhanced bank access flexibility for efficient data transfer in 7 Gb/s per pin IO bandwidth. The enhanced flexibility is achieved by elimination of bank group restriction and reduction of bank to bank active time to 2.5 ns. The effectiveness of these key features is verified by system model simulation including memory and its controller. To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control… CONTINUE READING

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