A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators

@article{Shu2012A63,
  title={A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators},
  author={Yun-Shiang Shu},
  journal={2012 Symposium on VLSI Circuits (VLSIC)},
  year={2012},
  pages={26-27}
}
A 6b 3GS/s fully dynamic flash ADC is fabricated in 40nm CMOS and occupies 0.021mm2. Dynamic comparators with digitally controlled built-in offset are realized with imbalanced tails. Half of the comparators are substituted with simple SR latches. The ADC achieves SNDRs of 36.2dB and 33.1dB at DC and Nyquist, respectively, while consuming 11mW from a 1.1V supply. 
Highly Cited
This paper has 56 citations. REVIEW CITATIONS

From This Paper

Figures, tables, and topics from this paper.

Citations

Publications citing this paper.
Showing 1-10 of 43 extracted citations

57 Citations

0102030'13'15'17
Citations per Year
Semantic Scholar estimates that this publication has 57 citations based on the available data.

See our FAQ for additional information.

References

Publications referenced by this paper.
Showing 1-3 of 3 references

and U

  • S. Weaver, B. Hershberg
  • Moon, “Digitally Synthesized Stochastic Flash ADC…
  • 2011
2 Excerpts

Similar Papers

Loading similar papers…