A 690-mW 1Gb / s 1024-b , Rate-1 / 2 Low-Density Parity-Check Code Decoder

@inproceedings{Blanksby2001A61,
  title={A 690-mW 1Gb / s 1024-b , Rate-1 / 2 Low-Density Parity-Check Code Decoder},
  author={Andrew J. Blanksby and Chris Howland},
  year={2001}
}
A 1024-b, rate-1/2, soft decision low-density paritycheck (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of 1 Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder switching activity resulting in a power dissipation of only 690 mW from a 1.5-V supply. 
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