A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI

Abstract

A 20 GS/s 6b time-interleaved ADC is implemented in 32 nm CMOS SOI with an embedded time-to-digital converter to sense timing skew, and the randomness of process mismatch is exploited to compensate for the clock misalignment and dynamic offset errors of comparators that occur during high-speed operation. To achieve low-power consumption at high-speed… (More)
DOI: 10.1109/JSSC.2014.2364043

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Cite this paper

@article{Chen2014A6M, title={A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI}, author={Vanessa H.-C. Chen and Lawrence T. Pileggi}, journal={IEEE Journal of Solid-State Circuits}, year={2014}, volume={49}, pages={2891-2901} }