A 65nm level-1 cache for mobile applications

Abstract

We describe L1 cache designed for QUALCOMM®'s latest-generation digital signal processor (DSP) core. The cache is 32KB with variable associativity (4 to 16 ways) and is pseudo-dual-ported. Dual access is achieved by banking the cache in a way that minimizes bank conflict to less than 1%. The cache operates at 600 MHZ under worst-case PVT conditions and… (More)

Topics

10 Figures and Tables

Slides referencing similar topics