A 65nm CMOS high-IF superheterodyne receiver with a High-Q complex BPF

@article{Madadi2013A6C,
  title={A 65nm CMOS high-IF superheterodyne receiver with a High-Q complex BPF},
  author={Iman Madadi and Massoud Tohidian and Robert Bogdan Staszewski},
  journal={2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)},
  year={2013},
  pages={323-326}
}
We propose a highly reconfigurable superheterodyne receiver that employs a 3rd-order complex IQ charge-sharing band-pass filter (BPF) for image rejection and 1st-order feedback based RF-BPF for channel selection filtering. The operating RF input frequency of the receiver is 500 MHz-1.2 GHz with varying high-IF range of 33-80 MHz. All the gain stages are merely inverter-based gm stages. The total gain of the receiver is 35dB and in-band IIP3 at midgain is +10 dBm. The NF of the receiver is 6.7dB… CONTINUE READING

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References

Publications referenced by this paper.
Showing 1-5 of 5 references

A low-power process-scalable superheterodyne receiver with integrated high-Q filters

2011 IEEE International Solid-State Circuits Conference • 2011
View 5 Excerpts
Highly Influenced

8-Path tunable RF notch filters for blocker suppression

2012 IEEE International Solid-State Circuits Conference • 2012
View 1 Excerpt

A 65 nm CMOS Quad-Band SAW-Less Receiver SoC for GSM/GPRS/EDGE

IEEE Journal of Solid-State Circuits • 2011
View 1 Excerpt

A Blocker Filtering Technique for SAW-Less Wireless Receivers

IEEE Journal of Solid-State Circuits • 2007
View 1 Excerpt

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