A 65 nm Ultra-High-Density Dual-Port SRAM with 0.71um/sup ~/ 8T-Cell for SoC

@article{Nii2006A6N,
  title={A 65 nm Ultra-High-Density Dual-Port SRAM with 0.71um/sup ~/ 8T-Cell for SoC},
  author={Koji Nii and Yuriko Masuda and Makoto Yabuuchi and Yasutaka Tsukamoto and Shigeki Ohbayashi and Susumu Imaoka and Mitsuhiko Igarashi and Kazutoshi Tomita and Nobuo Tsuboi and Hiroshi Makino and Koichiro Ishibashi and Hirofumi Shinohara},
  journal={2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.},
  year={2006},
  pages={130-131}
}
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71mum2 8T-DP-cell, which cell size is 1.44times larger than 6T-single-port (SP) cell 

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