A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

@article{Ohbayashi2007A6S,
  title={A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits},
  author={Shigeki Ohbayashi and Makoto Yabuuchi and Koji Nii and Yasumasa Tsukamoto and Susumu Imaoka and Yuji Oda and T. Yoshihara and Mitsuhiko Igarashi and Masahiko Takeuchi and Hisanobu Kawashima and Yukiharu Yamaguchi and Kenta Tsukamoto and Masahide Inuishi and Hiroshi Makino and Koichiro Ishibashi and Hirofumi Shinohara},
  journal={IEEE Journal of Solid-State Circuits},
  year={2007},
  volume={42},
  pages={820-829}
}
In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By… CONTINUE READING
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