A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU

@article{Ito2009A6N,
  title={A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU},
  author={Masayuki Ito and Kenichi Nitta and Koji Ohno and M. Saigusa and Michio Nishida and Shinichi Yoshioka and Takahiro Irita and Takao Koike and Tatsuya Kamei and Takako Komuro and Toshihiro Hattori and Yasuo Arai and Y. Kodama},
  journal={IEEE Journal of Solid-State Circuits},
  year={2009},
  volume={44},
  pages={83-89}
}
Supporting both WCDMA with HSDPA and GSM/GPRS/EDGE, the 9.3 times 9.3 mm2 SoC fabricated in triple-Vth 65 nm CMOS, has three CPU cores and 20 separate power domains. Unused power domains can be powered down to reduce the leakage power. Partial clock activation scheme especially focused on music playback scene dynamically stops a PLL and clock trees when not necessary and reduces power consumption from 33.6 mW to 19.6 mW. IP-MMU translates virtual address to physical address for 18 hardware-IPs… CONTINUE READING
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A 390 MHz single-chip application and dual-mode baseband processor in 90 nm triple-Vth CMOS

  • M. Ito
  • IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 274…
  • 2007
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