A 64Kb full CMOS RAM with divided word line structure

@article{Yoshimoto1983A6F,
  title={A 64Kb full CMOS RAM with divided word line structure},
  author={M. Yoshimoto and K. Anami and H. Shinohara and Takuya Yoshihara and H. Takagi and S. Nagao and S. Kayano and T. Nakano},
  journal={1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  year={1983},
  volume={XXVI},
  pages={58-59}
}
  • M. Yoshimoto, K. Anami, +5 authors T. Nakano
  • Published 1983
  • Computer Science
  • 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
  • An 8K×8b N-well CMOS static RAM with a divided word line architecture which decreases both the column current and word line delay will be described. The RAM achieves an access time of 50ns while dissipating 100mW. The use of molybdenum silicide as a substitute for the second polysilicon layer will be reviewed. 

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