A 64Kb full CMOS RAM with divided word line structure

@article{Yoshimoto1983A6F,
  title={A 64Kb full CMOS RAM with divided word line structure},
  author={Masahiko Yoshimoto and Kenji Anami and Hirofumi Shinohara and Tsutomu Yoshihara and H. Takagi and Shigeo Nagao and S. Kayano and T. Nakano},
  journal={1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  year={1983},
  volume={XXVI},
  pages={58-59}
}
  • M. Yoshimoto, K. Anami, +5 authors T. Nakano
  • Published 1983
  • Computer Science
  • 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
An 8K×8b N-well CMOS static RAM with a divided word line architecture which decreases both the column current and word line delay will be described. The RAM achieves an access time of 50ns while dissipating 100mW. The use of molybdenum silicide as a substitute for the second polysilicon layer will be reviewed. 
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A fully-static 8K×8b RAM using HICMOSII technology with a typical address access time of 65ns and power dissipation of 200mW will be discussed. To improve manufacturing yield a laser redundancy
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  • A. Ebel, G. Atwood, +5 authors Haiping Dun
  • Computer Science
    1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
  • 1982
TLDR
A 50ns 8K×8 static RAM developed with a double-poly/ scaled NMOS technology with a 64K die size will be reported.
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