A 64Kb full CMOS RAM with divided word line structure

  title={A 64Kb full CMOS RAM with divided word line structure},
  author={Masahiko Yoshimoto and Kenji Anami and Hirofumi Shinohara and Tsutomu Yoshihara and H. Takagi and Shigeo Nagao and S. Kayano and T. Nakano},
  journal={1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  • M. Yoshimoto, K. Anami, T. Nakano
  • Published 1983
  • Engineering
  • 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
An 8K×8b N-well CMOS static RAM with a divided word line architecture which decreases both the column current and word line delay will be described. The RAM achieves an access time of 50ns while dissipating 100mW. The use of molybdenum silicide as a substitute for the second polysilicon layer will be reviewed. 

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