A 64-bit decimal floating-point adder

@article{Thompson2004A6D,
  title={A 64-bit decimal floating-point adder},
  author={John D. Thompson and Nandini Karra and Michael J. Schulte},
  journal={IEEE Computer Society Annual Symposium on VLSI},
  year={2004},
  pages={297-298}
}
Due to rapid growth in financial, commercial, and Internet-based applications, there is an increasing desire to allow computers to operate on both binary and decimal floating-point numbers. Consequently, specifications for decimal floating-point support are being added to the IEEE-754 Standard for Floating-Point Arithmetic. In this paper, we present the design and implementation of a decimal floating-point adder that is compliant with the current draft revision of this standard. The adder… CONTINUE READING
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