A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

@article{Pilo2012A6M,
  title={A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements},
  author={Harold Pilo and Igor Arsovski and Kevin Batson and Geordie Braceras and John Gabric and Robert M. Houle and Steve Lamphier and Carl Radens and Adnan Seferagic},
  journal={IEEE Journal of Solid-State Circuits},
  year={2012},
  volume={47},
  pages={97-106}
}
A 64 Mb SRAM macro has been fabricated in a 32 nm high-k metal-gate SOI technology. The SRAM features a 0.154 μm2 bit-cell, the smallest to date for a 32 nm SOI product. A 0.7 V VDDMIN operation is enabled by three assist features. Stability is improved by a bit-line regulation scheme which reduces charge injection into the bit-cell. Enhancements to the write path include an increase of 40% of bit-line boost voltage. Finally, a bit-cell-tracking delay circuit improves both performance and yield… CONTINUE READING

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