A 60ns 4Mb DRAM in a 300mil DIP

  title={A 60ns 4Mb DRAM in a 300mil DIP},
  author={T. Sumi and T. Taniguchi and M. Kishimoto and H. Hirano and H. Kuriyama and T. Nishimoto and H. Oishi and S. Tetakawa},
  journal={1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  • T. Sumi, T. Taniguchi, +5 authors S. Tetakawa
  • Published 1987
  • Computer Science
  • 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
THIS PAPER WILL DESCRIBE A 4Mb CMOS DRAM with a 60ns RAS access time and 4.54mm x 1.4.78mm (67.1mm2) chip area assembled in a 300mil dual-in-line plastic package. The RAM has been fabricated in a twin-tub CMOS process technology with double-poly, single-polycide and single-metal using a 0 . 8 ~ design rule. One of the key technologies to program in developing a 4Mb DRAM in a 300mil DIP is to produce stable small-size memory cells free from leakage current between adjacent cells. The leakage… Expand
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