A 600 MHz VLIW DSP

@article{Agarwala2002A6M,
  title={A 600 MHz VLIW DSP},
  author={Sanjive Agarwala and Peter Koeppen and Theodore W. Anderson and Anita Hill and Mike Ales and Raguram Damodaran and Lewis Nardini and Paul Wiley and Steven Mullinnix and Jessica Leach and Alfred Lell and Mike Gill and Jeremiah Golston and David Hoyle and Arjun Rajagopal and Abhijeet Chachad and M. Agarwala and Ren{\'e} Castille and Neil Common and John Apostol and Hisham Mahmood and Manjeri Krishnan and Duc Bui and Quang-Dieu An and Peter Groves and Loi Nguyen and N. S. Nagaraj and Ray Simar},
  journal={2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)},
  year={2002},
  volume={1},
  pages={56-444 vol.1}
}
A 600 MHz VLIW DSP, which implements the C64x VelociTI.2/spl trade/ architecture delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates at 0.3 mW/MMAC (16 b). The chip has 64 M transistors and dissipates 718 mW at 600 MHz and 1.2 V, and 200 mW at 300 MHz and 0.9 V. It has an 8-way VLIW DSP core, a 2-level memory system, and 2.4 GB/s I/O bandwidth. The DSP chip is implemented in 0.13 μm CMOS technology with 6-layer copper metalization. 
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