A 60 mW 10 b CMOS image sensor with column-to-column FPN reduction

@article{Sugiki2000A6M,
  title={A 60 mW 10 b CMOS image sensor with column-to-column FPN reduction},
  author={T. Sugiki and Susumu Ohsawa and Hisashi Miura and Masahide Sasaki and Norihiro Nakamura and Ikuo Inoue and Mikio Hoshino and Yasushi Tomizawa and Takahiro Arakawa},
  journal={2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)},
  year={2000},
  pages={108-109}
}
A 60 mW 10b 660(H)/spl times/490(v) pixel digital CMOS image sensor with column-to-column FPN reduction introduces the double inverting amplifier with double clamp circuit for reduction of column-to-column fixed pattern noise (dark FPN and light FPN). It operates with a 3.3 V power supply and has 60 mW power consumption. This sensor is uses 0.6 /spl mu/m, triple-poly-silicon, double-metal CMOS technology. 
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