A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

@article{Rossi2016A6G,
  title={A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology},
  author={D. Rossi and Antonio Pullini and Igor Loi and Michael Gautschi and Frank K. G{\"u}rkaynak and Andrea Bartolini and P. Flatresse and L. Benini},
  journal={Solid-state Electronics},
  year={2016},
  volume={117},
  pages={170-184}
}
Abstract Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human–Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance… Expand
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Sub-pJ per operation scalable computing: The PULP experience
  • D. Rossi
  • Engineering
  • 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
  • 2016
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