A 6.25Gb/s Decision Feedback Equalizer in 0.18¥im CMOS Technology for High-Speed SerDes

Abstract

In this paper a 6.25Gb/s two-tap half-rate decision feedback equalizer (DFE) is designed and implemented in TSMC 0.18¥im CMOS technology. After system-level simulation based on Simulink and pre-simulation, the DFE architecture is designed and corresponding parameters are determined. To achieve high data rate, CML DFFs, summers and multiplex are all designed… (More)

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