A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization

@article{Vangal2006A6F,
  title={A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization},
  author={S. R. Vangal and Y. Hoskote and N. Borkar and Atila Alvandpour},
  journal={IEEE Journal of Solid-State Circuits},
  year={2006},
  volume={41},
  pages={2314-2323}
}
A pipelined single-precision floating-point multiply-accumulator (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save arithmetic with delayed addition is described. A combination of algorithmic, logic, and circuit techniques enables multiply-accumulate operations at speeds exceeding 3 GHz with single-cycle throughput. The optimizations allow removal of the costly normalization step from the critical accumulate loop. This logic is conditionally powered down… CONTINUE READING
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