A 6 mW, 5,000-Word Real-Time Speech Recognizer Using WFST Models

@article{Price2015A6M,
  title={A 6 mW, 5,000-Word Real-Time Speech Recognizer Using WFST Models},
  author={Michael Price and James R. Glass and Anantha Chandrakasan},
  journal={IEEE Journal of Solid-State Circuits},
  year={2015},
  volume={50},
  pages={102-112}
}
We describe an IC that provides a local speech recognition capability for a variety of electronic devices. We start with a generic speech decoder architecture that is programmable with industry-standard WFST and GMM speech models. Algorithm and architectural enhancements are incorporated in order to achieve real-time performance amid system-level constraints on internal memory size and external memory bandwidth. A 2.5 × 2.5 mm test chip implementing this architecture was fabricated using a 65… CONTINUE READING
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  • The chip performs a 5,000 word recognition task in real-time with 13.0% word error rate, 6.0 mW core power consumption, and a search efficiency of approximately 16 nJ per hypothesis.

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