A 6-bit 800MS/s flash ADC in 0.35μm CMOS

@article{Ghasemzadeh2015A68,
  title={A 6-bit 800MS/s flash ADC in 0.35μm CMOS},
  author={Mehdi Ghasemzadeh and Arefeh Soltani and Amin Akbari and Khayrollah Hadidi},
  journal={2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)},
  year={2015},
  pages={234-238}
}
In this work, a 6-bit 800 MS/s flash analog-to-digital converter (ADC) is proposed. An optimized resistance ratio averaging scheme is applied to: (1) reduce the offset, nonlinearity, (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors. The proposed ADC is simulated by Hspice using 0.35 μm TSMC… CONTINUE READING

References

Publications referenced by this paper.
SHOWING 1-10 OF 39 REFERENCES

A novel technique for wideband bipolar amplifiers

  • 2013 21st Iranian Conference on Electrical Engineering (ICEE)
  • 2013
VIEW 4 EXCERPTS

A 6-bit 1.6 GS/s Flash ADC in 0.18-μm CMOS with Reversed-Reference Dummy

  • 2006 IEEE Asian Solid-State Circuits Conference
  • 2006
VIEW 4 EXCERPTS
HIGHLY INFLUENTIAL

A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme

  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2010
VIEW 3 EXCERPTS

A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS

  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • 2008
VIEW 2 EXCERPTS

A novel flash analog-to-digital converter

  • 2008 IEEE International Symposium on Circuits and Systems
  • 2008

A 43 mW single - channel 4 GS / s 4 - bit Flash ADC in O . 18m CMOS , IEEE Custom Integr

M. Kuijk, G. Van der Plas
  • Symp . VLSI Circuits Digest of Technical Papers
  • 2007