A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC

  title={A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC},
  author={C. Chan and Yan Zhu and Sai-Weng Sin and U. Seng-Pan and R. Martins},
  journal={IEEE Journal of Solid-State Circuits},
This paper presents a 4× time-interleaved 6-bit 5 GS/s 3 b/cycle SAR analog-to-digital converter (ADC). Hardware overhead induced by a 3 b/cycle architecture is eased by an interpolation technique where around 1/3 of the hardware is saved. In addition, complicated switching controls are simplified with a proposed fractional DAC array switching scheme, thus reducing the design complexity and the hardware burden. A boundary detection code overriding (BDCO) is introduced to reduce error… Expand
20 Citations
A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler
A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration
  • Highly Influenced
A 12-bit 150-MS/s Sub-Radix-3 SAR ADC With Switching Miller Capacitance Reduction
  • 4
A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration
  • 22
  • PDF
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique
A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration
  • 1
A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration
  • 4
A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier


A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS
  • 56
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS
  • 204
  • PDF
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC
  • 16
  • PDF
A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control
  • 36
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC
  • 76
  • PDF
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure
  • 53
22.4 A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration
  • 30
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
  • 481
  • PDF