A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC

@article{Chan2016A6B,
  title={A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC},
  author={C. Chan and Yan Zhu and Sai-Weng Sin and U. Seng-Pan and R. Martins},
  journal={IEEE Journal of Solid-State Circuits},
  year={2016},
  volume={51},
  pages={365-377}
}
This paper presents a 4× time-interleaved 6-bit 5 GS/s 3 b/cycle SAR analog-to-digital converter (ADC). Hardware overhead induced by a 3 b/cycle architecture is eased by an interpolation technique where around 1/3 of the hardware is saved. In addition, complicated switching controls are simplified with a proposed fractional DAC array switching scheme, thus reducing the design complexity and the hardware burden. A boundary detection code overriding (BDCO) is introduced to reduce error… Expand
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