A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS

@article{Kim2013A64,
  title={A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS},
  author={Jong-In Kim and Ba-Ro-Saim Sung and Wan Kim and Seung-Tak Ryu},
  journal={IEEE Journal of Solid-State Circuits},
  year={2013},
  volume={48},
  pages={1429-1441}
}
A 6-b 4.1-GS/s flash ADC was fabricated using a 90-nm CMOS with a time-domain latch interpolation technique that reduces the number of front-end dynamic comparators by half. The reduced number of comparators lowers power consumption, load capacitance to the T/H circuit, and the overhead of comparator calibration. The measured peak INL and DNL after comparator calibration are 0.74 and 0.49 LSB, respectively. The measured SNDR and SFDR are 31.2 and 38.3 dB, respectively, with a 2.02-GHz input at… CONTINUE READING
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