A 5GHz fully integrated super-regenerative receiver with on-chip slot antenna in 0.13μm CMOS

@article{Shi2008A5F,
  title={A 5GHz fully integrated super-regenerative receiver with on-chip slot antenna in 0.13μm CMOS},
  author={Dan Shi and Nader Behdad and Jia-Yi Chen and M. P. Flynn},
  journal={2008 IEEE Symposium on VLSI Circuits},
  year={2008},
  pages={34-35}
}
A single chip receiver based on super-regeneration incorporates an on-chip slot antenna and digital received data synchronization. A capacitively-loaded standing-wave resonator improves energy efficiency. An all-digital PLL timing scheme synchronizes the received data clock. The prototype 5 GHz receiver, implemented in 0.13 mum CMOS, achieves a data rate of up to 1.2 Mb/s, dissipates 6.6 mW from a 1.5 V supply, and occupies a die area of 2.4 mm2. 
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