A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

@article{Chung2011A51,
  title={A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW},
  author={Hoeju Chung and Byung Hoon Jeong and ByungJun Min and Youngdon Choi and Beak-Hyung Cho and Junho Shin and Jinyoung Kim and Jung Sunwoo and Joon-min Park and Qi Wang and Yong-jun Lee and Sooho Cha and Dukmin Kwon and Sangtae Kim and Sunghoon Kim and Yoohwan Rho and Mu-Hui Park and Jaewhan Kim and Ickhyun Song and Sung-Bu Jun and Jaewook Lee and KiSeung Kim and Ki-won Lim and Won-ryul Chung and ChangHan Choi and Ho-Keun Cho and In-Cheol Shin and Woo-Jung Jun and Seokwon Hwang and Ki-Whan Song and Kwangjin Lee and Sang-whan Chang and Woo-Yeong Cho and Jei-Hwan Yoo and Young-Hyun Jun},
  journal={2011 IEEE International Solid-State Circuits Conference},
  year={2011},
  pages={500-502}
}
  • Hoeju ChungB. Jeong Y. Jun
  • Published 7 April 2011
  • Computer Science
  • 2011 IEEE International Solid-State Circuits Conference
In mobile systems, the demand for the energy saving continues to require a low power memory sub-system. During the last decade, the floating-gate flash memory has been an indispensable low power memory solution. However, NOR flash memory has begun to show difficulties in scaling due to the device's reliability and yield issues. Over the past few years, phase-change random access memory (PRAM) has emerged as an alternative non-volatile memory (NVM) owing to its promising scalability and low cost… 

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

An 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells is presented and when an external high voltage is applied, the write bandwidth can be extended as high as 133 MB/s.

Accelerating Memory Access with Address Phase Skipping in LPDDR2-NVM

This paper proposes address phase skipping by reforming the way of interfacing with LPDDR2-NVM, and develops a system-level prototype that includes the authors' customized LPD DR2- NVM controller and commercial PCM devices.

A Sequential Write Scheme for Phase Change Memory Based Serial Interface EEPROM

A 1Mb Serial EEPROM compatible non-volatile memory (NVM) with phase change memory (PCM) device has been developed in 40nm CMOS technology and a sequential shift write scheme is proposed that reduces the maximum SET and RESET write current.

A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications

For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory

An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput

An 8Mb multi-layered cross-point ReRAM macro with 443MB/S write throughput is developed, which is almost twice as fast as existing methods, using the fast-switching performance of TaOχ ReRAM and the following three techniques to reduce the sneak current in bipolar type cross- point cell array structure in an 0.18μm process.

Throughput Enhancement for Phase Change Memories

This paper develops a non-blocking PCM bank design such that subsequent reads or writes can be carried in parallel with an on-going write, effective in removing long blocking time due to serial operations and proposes novel memory request scheduling algorithms to exploit intra-bank parallelism brought by the non- blocking hardware.

A reliable, secure phase-change memory as a main memory

It is argued that a PCM design not only has to consider normal wear-out under normal application behavior, but also must take the worst-case scenario into account with the presence of malicious exploits and a compromised OS to address the durability and security issues simultaneously.

Design and Optimization of Nonvolatile Multibit 1 T 1 R Resistive RAM

Memristor-based random access memory (RAM) is being explored as a potential replacement for flash memory to sustain the historic trends in the improvement of density, access time, and energy

Power of One Bit: Increasing Error Correction Capability with Data Inversion

This paper proposes data inversion as a practical technique to increase the number of faults that an error correction code can cover and extends the lifetime of phase-change memory by up to 34.5%.
...

References

SHOWING 1-2 OF 2 REFERENCES

A 45nm 1Gb 1.8V phase-change memory

Floating-gate Flash memories have been able so far to satisfy the market requirements, especially for the portable equipments, and to be the mainstream non-volatile memory (NVM) technology [1].

A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput

A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are described, which achieves read throughput of 266MB/S and maximum write throughput of 4.64 MB/S with a 1.8V supply.