A 56-entry instruction reorder buffer

@article{Gaddis1996A5I,
  title={A 56-entry instruction reorder buffer},
  author={N Gaddis and J. R. Butler and Amrish Kumar and W D Queen},
  journal={1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC},
  year={1996},
  pages={212-213}
}
A speculative execution high-end PA-RISC CPU has two 28-entry out-of-order instruction reorder buffers (IRBs), one for alu/floating point operations and one for memory operations. The IRBs are capable of inserting any combination of four instructions per cycle. Each cycle, the IRBs launch up to four instructions for execution, two from the ALU IRB and two from the MEM IRB. Up to four instructions (two from each IRB) retire each cycle. The insert, launch and retire mechanisms of this out-of… CONTINUE READING