A 550MHz 9.3mW CMOS Frequency Divider

@inproceedings{Wu1995A59,
  title={A 550MHz 9.3mW CMOS Frequency Divider},
  author={Jiin-Chuan Wu and Hun-Hsien Chang},
  booktitle={ISCAS},
  year={1995}
}
This paper deals with the design of a high speed CMOS programmable frequency counter design. It is the heart of a frequency synthesizer IC. By using an end-ofcount (EOC) detecting algorithm, and a modified ripple down counter, we designed a high performance 14-bits programmable counter. The programming values N can be from 3 to 16384. The chip is… CONTINUE READING