A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques

@article{Park2006A5D,
  title={A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques},
  author={Churoo Park and HoeJu Chung and Yun-Sang Lee and Jaekwan Kim and JaeJun Lee and Moo-Sung Chae and Dae-Hee Jung and Sung-Ho Choi and Seung-young Seo and Taek-Seon Park and Jun-Ho Shin and Jin-Hyung Cho and Seunghoon Lee and Ki-Whan Song and Kyu-hyoun Kim and Jung-Bae Lee and Changhyun Kim and Soo-In Cho},
  journal={IEEE Journal of Solid-State Circuits},
  year={2006},
  volume={41},
  pages={831-838}
}
A 1.5-V 512-Mb DDR3 synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and C/sub IO/ minimization, which were achieved by on-die-termination (ODT)-merged output drivers, SCR type ESD protection, and self-calibration scheme. The hybrid latency control scheme can turn the DLL off in standby mode, reducing power consumption. User-friendly functions such as… CONTINUE READING
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