A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps

@article{Ahmed2009A59,
  title={A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps},
  author={Imran Ahmed and Jan Mulder and David A. Johns},
  journal={2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers},
  year={2009},
  pages={164-165,165a}
}
In the interest of extending battery life in mobile systems that use pipelined ADCs, several power-efficient pipelined ADCs have recently been proposed. The most promising topologies reported thus far are those that substitute the opamp, which is the largest consumer of power in pipelined ADCs, with alternative and more power-efficient circuits. However, opamp-less pipelined ADCs thus far either: 1) require complex nonlinear calibration [1], 2) are single-ended [2], 3) are pseudo-differential… CONTINUE READING
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