A 500MS/s 5b ADC in 65nm CMOS

@article{Ginsburg2006A55,
  title={A 500MS/s 5b ADC in 65nm CMOS},
  author={B. P. Ginsburg and A. P. Chandrakasan},
  journal={2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.},
  year={2006},
  pages={140-141}
}
  • B.P. Ginsburg, A. P. Chandrakasan
  • Published in
    Symposium on VLSI Circuits…
    2006
  • Computer Science
  • A 1.2V 6mW 500MS/s 5-bit ADC for use in a UWB receiver has been fabricated in a pure digital 65nm CMOS technology. The ADC uses a 6-channel time-interleaved successive approximation register architecture. Each of the channels has a split capacitor array to reduce switching energy and sensitivity to digital timing skew. A variable delay line is used to optimize the instant of latch strobing to reduce preamplifier currents 

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