A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

@article{Zhu2012A51,
  title={A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation},
  author={Yan Zhu and C. Chan and Sai-Weng Sin and U. Seng-Pan and R. Martins and F. Maloberti},
  journal={IEEE Journal of Solid-State Circuits},
  year={2012},
  volume={47},
  pages={2614-2626}
}
This paper presents a time-interleaved pipelined-SAR ADC with on-chip offset cancellation technique. The design reuses the SAR ADC to perform offset cancellation, thus saving calibration costs. The inter-stage gain of 8 is implemented in a 6-bit capacitive DAC with a flip-around operation. A capacitive attenuation used in both the first and second DACs significantly reduces the power dissipation and optimizes conversion speed. The detailed circuit implementation of the subthreshold op-amp is… Expand
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