A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS

@article{Rodoni2009A5T,
  title={A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS},
  author={Lucio Rodoni and George von B{\"u}ren and Alex Huber and Martin L. Schmatz and Heinz J{\"a}ckel},
  journal={IEEE Journal of Solid-State Circuits},
  year={2009},
  volume={44},
  pages={1927-1941}
}
This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2times-oversampling phase-tracking CDR, implemented in 90 nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with eight parallel differential master-slave flip-flops, where bandwidth enhancement techniques were necessary for 90 nm CMOS. Precise and low… CONTINUE READING

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