A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor

@article{Davis2006A56,
  title={A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor},
  author={Jonathan Davis and Donald W. Plass and Paul Bunce and Y. Chan and A. Pelella and R. V. Joshi and Ann Chen and W. Huott and Thomas J. Knips and Pradip Patel and Kueiming Lo and Eric Fluhr},
  journal={2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers},
  year={2006},
  pages={2564-2571}
}
A dual-read 8-way set-associative data cache comprising four 16kB SRAMs and 2 set-prediction macros per P0WER6 core is presented. The array utilizes a 0.75mum2 butted-junction split-word line 6T cell in 65nm SOI. The design features dual power supplies, unidirectional polysilicon, and hierarchical undamped bit lines for enhanced cell stability and performance 
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