A 5.1mW 74dB DR CT ΔΣ modulator with quantizer intrinsic ELD compensation achieving 75fJ/conv.-step in a 20MHz BW

@article{Ding2015A57,
  title={A 5.1mW 74dB DR CT ΔΣ modulator with quantizer intrinsic ELD compensation achieving 75fJ/conv.-step in a 20MHz BW},
  author={Chongjun Ding and Yiannos Manoli and Matthias Keller},
  journal={ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)},
  year={2015},
  pages={213-216}
}
A third-order continuous-time Delta-Sigma modulator in a 130 nm CMOS technology is presented. It features a 3-bit quantizer with an intrinsic excess loop delay compensation for half a clock cycle. The compensation is performed by means of adapting the reference voltages of the comparators on a sampling-to-sampling base, thus overcoming a power consuming summation of signals in front of the quantizer. Occupying merely 0.086mm2, the modulator achieves 66.4 dB SNDR and 74.6 dB DR in a 20 MHz… CONTINUE READING

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A 20mW 640MHz CMOS Continuous-Time ΔΣ ADC With 20MHz Signal Bandwidth 80dB Dynamic Range and 12-bit ENOB

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IEEE J. Solid-State Circuits, • 2006
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