A 5-mW 0.26-mm2 10-bit 20-MS/s Pipelined CMOS ADC with Multi-Stage Amplifier Sharing Technique

Abstract

This paper describes a 10-bit 20-Msample/s analog-to-digital converter (ADC) employing a multi-stage amplifier sharing scheme to reduce the power consumption and chip area at low supply voltages. The proposed scheme shares a multi-stage amplifier between a sample-and-hold amplifier and a first-stage multi-bit multiplying digital-to-analog converter by… (More)

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