A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS

@article{Lin2007A54,
  title={A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS},
  author={Ying-Zu Lin and Yen-Ting Liu and Soon-Jyh Chang},
  journal={2007 IEEE Custom Integrated Circuits Conference},
  year={2007},
  pages={213-216}
}
A compact 5-bit flash ADC is designed and fabricated in TSMC 0.13-μm CMOS process. Resistive averaging network and interpolation are discussed and analyzed for power reduction. This proposed ADC consumes 180 mW from a 1.2 V supply and occupies 0.16 mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.51 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively. 
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