A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

@article{Mistry2007A4L,
  title={A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100\% Pb-free Packaging},
  author={Kaizad R. Mistry and Craig Allen and Chris Auth and B. Beattie and D. Bergstrom and M. Bost and M. Brazier and Marc Buehler and Annalisa Cappellani and Robert Chau and Chae Hyoung Choi and G. Ding and Kevin Fischer and Tahir Ghani and Rohit Grover and W. Han and Dennis G. Hanken and Michael L. Hattendorf and J. He and Jeff Hicks and R. Huessner and Doug B. Ingerly and Pulkit Jain and R. James and L. Jong and S. Joshi and C. Kenyon and Kelin J. Kuhn and K. S. Lee and H. Liu and Jose Maiz and B G Mclntyre and Peter Moon and Johan Neirynck and Sangwoo Pae and C. Parker and D. Parsons and Chetan Prasad and Leonard C. Pipes and M. Prince and P. Ranade and T. Reynolds and Justin S. Sandford and Lucian Shifren and Javier Sebasti{\'a}n and J. Seiple and D. Simon and S. Sivakumar and P. Smith and C. Thomas and Thomas H. Troeger and Peter Vandervoorn and S. Williams and Keith Zawadzki},
  journal={2007 IEEE International Electron Devices Meeting},
  year={2007},
  pages={247-250}
}
A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry… 

Figures from this paper

Metal Gate Strain-Enhanced Transistors 77 Process and Electrical Results for the On-die Interconnect 87
For the 45nm technology node, high-k+metal gate transistors have been introduced for the first time in a high-volume manufacturing process [1]. The introduction of a high-k gate dielectric enabled a
45nm high-k + metal gate strain-enhanced CMOS transistors
  • C. Auth
  • Engineering
    2008 IEEE Custom Integrated Circuits Conference
  • 2008
TLDR
Dual-band edge workfunction metal gates were introduced, eliminating polysilicon gate depletion and providing compatibility with the high-k gate dielectric, and have demonstrated the highest drive currents to date for both NMOS and PMOS.
22-nm fully-depleted tri-gate CMOS transistors
  • C. Auth
  • Engineering
    Proceedings of the IEEE 2012 Custom Integrated Circuits Conference
  • 2012
TLDR
At the 22-nm technology node, fully-depleted tri-gate transistors were introduced for the first time on a high-volume manufacturing process resulting in the highest drive currents yet reported for NMOS and PMOS.
Reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging
TLDR
Integrated product defect reliability results are presented showing that the historical correlation to yield defect density for stable manufacturing processes is maintained on this generation into an even lower fail rate regime.
Gate-first high-k/metal gate DRAM technology for low power and high performance products
It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was
45nm High-k + metal gate strain-enhanced transistors
Two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of
32nm gate-first high-k/metal-gate technology for high performance low power applications
A 32 nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 muA/mum (n/p) are achieved at
High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High- $\kappa $ /Metal Gate
We present a vertical gate-all-around Si nanowire (SiNW) metal-oxide-semiconductor field-effect transistor with high-κ dielectric and TiN metal gate. The process flow is fully compatible with CMOS
Low-K Interconnect Stack with Thick Metal 9 Redistribution Layer and Cu Die Bump for 45nm High Volume Manufacturing
Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive
Performance Analysis of Sub-22nm Metal Gate Fully Depleted SOI MOSFET with High-K Gate Dielectric
With the growing technology, the density of transistors on chips has been periodically doubling, as predicted by Moore’s Law. In order to achieve this, the device dimensions have been continuously
...
1
2
3
4
5
...

References

SHOWING 1-10 OF 16 REFERENCES
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell
  • P. Bai, C. Auth, M. Bohr
  • Engineering
    IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.
  • 2004
A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is
An advanced low power, high performance, strained channel 65nm technology
  • S. Tyagi, C. Auth, K. Tone
  • Engineering
    IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.
  • 2005
An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents of
Review on high-k dielectrics reliability issues
High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve
High- /Metal-Gate Stack and Its MOSFET Characteristics
We show experimental evidence of surface phonon scattering in the high- dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN metal-gate electrode
High-/spl kappa//metal-gate stack and its MOSFET characteristics
We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN
Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology
We describe the device physics of uniaxial strained silicon transistors. Uniaxial strain is more effective, less costly and easier to implement. The highest PMOS drive current to date is reported:
Inversion mobility and gate leakage in high-k/metal gate MOSFETs
  • R. Kotlyar, M. Giles, E. Wang
  • Engineering
    IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.
  • 2004
For the first time, we show with simulation that the use of a metal gate/high-k stack offers improved mobility over polysilicon/high-k gates stacks while maintaining decreased gate leakage compared
Issues in High-ĸ Gate Stack Interfaces
We address current challenges in the fundamental understanding of physical and chemical processes that occur in the fabrication of the transistor gate stack structure. Critical areas include (1) the
Fermi level pinning at the polySi/metal oxide interface
  • C. Hobbs, L. Fonseca, P. Tobin
  • Physics
    2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)
  • 2003
We report here for the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial
Impact of oxygen vacancies on high-/spl kappa/ gate stack engineering
The impact of oxygen vacancies in Hf-based gate dielectrics is discussed. Generation of oxygen vacancies in HfO/sub 2/ is thermodynamically driven and causes Si interfacial layer formation and gate
...
1
2
...