A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
@article{Mistry2007A4L,
title={A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100\% Pb-free Packaging},
author={Kaizad R. Mistry and Craig Allen and Chris Auth and B. Beattie and D. Bergstrom and M. Bost and M. Brazier and Marc Buehler and Annalisa Cappellani and Robert Chau and Chae Hyoung Choi and G. Ding and Kevin Fischer and Tahir Ghani and Rohit Grover and W. Han and Dennis G. Hanken and Michael L. Hattendorf and J. He and Jeff Hicks and R. Huessner and Doug B. Ingerly and Pulkit Jain and R. James and L. Jong and S. Joshi and C. Kenyon and Kelin J. Kuhn and K. S. Lee and H. Liu and Jose Maiz and B G Mclntyre and Peter Moon and Johan Neirynck and Sangwoo Pae and C. Parker and D. Parsons and Chetan Prasad and Leonard C. Pipes and M. Prince and P. Ranade and T. Reynolds and Justin S. Sandford and Lucian Shifren and Javier Sebasti{\'a}n and J. Seiple and D. Simon and S. Sivakumar and P. Smith and C. Thomas and Thomas H. Troeger and Peter Vandervoorn and S. Williams and Keith Zawadzki},
journal={2007 IEEE International Electron Devices Meeting},
year={2007},
pages={247-250}
}A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry…
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