A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons


Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of analog neuron circuits; (b) the enormous area overhead of learning circuits, which grows with the number of synapses; and (c) the need to implement all inter-neuron communication… (More)
DOI: 10.1109/CICC.2011.6055293


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