A 45nm 24MB on-die L3 cache for the 8-core multi-threaded Xeon® Processor

@article{Chang2009A42,
  title={A 45nm 24MB on-die L3 cache for the 8-core multi-threaded Xeon® Processor},
  author={Jonathan Chang and Szu-Liang Chen and Wei Chen and Siufu Chiu and Robert Faber and Raghuraman Ganesan and Marijana Grgek and Venkata Lukka and Wei Wing Mar and James Vash and Stefan Rusu and Kevin Zhang},
  journal={2009 Symposium on VLSI Circuits},
  year={2009},
  pages={152-153}
}
The 24-way set associative 24MB 8-ported L3 cache for the 8-core Xeon® Processor uses 0.3816 µm02 cell in a 45nm high-K dielectric metal gate technology 9-copper layers. It is protected by double-error correction/triple-error detection ECC. The basic building block is designed to support completely different floorplan styles on 2 processors with large L3 cache. Off die fuse storage enables high resolution repair coverage. 
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