A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance

@article{Kim2011A41,
  title={A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance},
  author={Jung Pill Kim and Taehyun Kim and Wuyang Hao and H. Ram Mohan Rao and Kangho Lee and Xiaochun Zhu and Xia Li and Wah Hsu and Seung H. Kang and Nowak Matt and Nick Yu},
  journal={2011 Symposium on VLSI Circuits - Digest of Technical Papers},
  year={2011},
  pages={296-297}
}
1Mb embedded STT-MRAM macro using 45nm CMOS process includes two key design features; a dual-voltage row decoder with a charge sharing scheme for read operations and a sensing circuit with two equalizers and read-disturbance-free reference cells. These designs minimize read-disturbance and achieve fast read operation. 
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