A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist

@article{Yabuuchi2009A40,
  title={A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist},
  author={Makoto Yabuuchi and Koji Nii and Yasumasa Tsukamoto and Shigeki Ohbayashi and Yasunobu Nakase and Hirofumi Shinohara},
  journal={2009 Symposium on VLSI Circuits},
  year={2009},
  pages={158-159}
}
We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. A negative bias technique for VSS and bitline (BL) enables us to achieve not only low power and high access speed, but also the large cell stability and write ability. Using 45-nm CMOS technology, we fabricated the SRAM macro based on our… CONTINUE READING

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