A 450 MHz 512 kB second-level cache with a 3.6 GB/s data bandwidth

@article{Bateman1998A4M,
  title={A 450 MHz 512 kB second-level cache with a 3.6 GB/s data bandwidth},
  author={Bruce L. Bateman and C. Freeman and John B. Halbert and K. Hose and Gene Petrie and E. Reese},
  journal={1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)},
  year={1998},
  pages={358-359}
}
  • B. Bateman, C. Freeman, E. Reese
  • Published 5 February 1998
  • Computer Science
  • 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)
This 512 kB, 4-way set-associative cache SRAM for a processor is configurable as a 512 k, or larger, second-level cache using one or more cache chips. Speed between the processor and cache in separate packages is achieved by communicating over an independent source-synchronous 72 b data bus. Power is reduced by semi-synchronous design. Supply voltage is 2.5 V and maximum core power is 4.5 W at 450 MHz assuming back-to-back reads. The 0.35 /spl mu/m CMOS process features 4-level metal and a 0.22… 

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References

A 450 MHz IA32 P6 family microprocessor
  • J. Schutz, R. Wallace
  • Computer Science, Engineering
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  • 1998
TLDR
This implementation adds new support for back side bus caches that transfer data at the core clock rate in 1 MB and 2 MB implementations to support 4-way servers.