A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

Abstract

We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands… (More)

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@article{Nii2008A4S, title={A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment}, author={K. Nii and Masayoshi Yabuuchi and Y. Tsukamoto and Shiran Ohbayashi and Y. Oda and K. Usui and T. Kawamura and Narumi Tsuboi and T Iwasaki and K. Hashimoto and H. Makino and H. Shinohara}, journal={2008 IEEE Symposium on VLSI Circuits}, year={2008}, pages={212-213} }