A 433 MHz 64 b quad issue RISC microprocessor

  title={A 433 MHz 64 b quad issue RISC microprocessor},
  author={Paul E. Gronowski and Peter J. Bannon and R.P. Blake-Campos and Gregg A. Bouchard and William J. Bowhill and D. Carlson and Ruben W. Castelino and Dale R. Donchin and Richard Fromm and M. Gowan and A.K. Jain and B.J. Loughlin and Shekhar Mehta and J.E. Meyer and R. O. Mueller and A. Olesin and Tung N. Pham and Ronald P. Preston and Paul I. Rubinfeld},
  journal={1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC},
  • P. Gronowski, P. Bannon, +16 authors P. Rubinfeld
  • Published 8 February 1996
  • Computer Science
  • 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC
This 9.6 M transistor quad-issue RISC microprocessor achieves greater than 500 SPECint92 (estimated) at 433 MHz. The die measures 14.5/spl times/14.4 mm/sup 2/ fabricated in a 0.35 /spl mu/m CMOS process. The chip uses split-power supplies; the core operates at 2.0 V and the external interface at 3.3 V. The chip dissipates less than 25 W. 
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