A 40GS/s 6b ADC in 65nm CMOS

@article{Greshishchev2010A46,
  title={A 40GS/s 6b ADC in 65nm CMOS},
  author={Yuriy M. Greshishchev and Jorge Aguirre and Marinette Besson and Robert Gibbins and Chris Falt and Philip Flemke and Naim Ben-Hamida and Daniel Pollex and Peter Schvan and Shing-Chi Wang},
  journal={2010 IEEE International Solid-State Circuits Conference - (ISSCC)},
  year={2010},
  pages={390-391}
}
Progress in 40Gb/s optical dual- polarization (DP) QPSK systems inspired an idea of 100G transmission by optical frequency division multiplexing (FDM) of QPSK-modulated channels [1]. A practical solution suggests two 58Gb/s DP QPSK channels, spaced by 50GHz (Fig. 21.7.1). The challenge is in implementing a 6b ADC operating at sampling rate of 29Gs/s, as compared to 24Gs/s reported before [2]. The other challenge is reduction of ADC sampling jitter. In an interleaved architecture, jitter is… CONTINUE READING
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Real Time 40 Gb/s Coherent System

  • Kim Roberts
  • Coherent Optical Technologies and Applications…
  • 2008
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